Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM [1] describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.
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The upper buried word line may be formed by forming a second word line layer not shown on the substrate so as to bury the trench including the lower buried word line Semiconductor having buried word line cell structure and method of fabricating the same.
Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. In example embodiments, the lower buried word line may include polysilicon.
Recently, there has been increasing research on the buried word line cell array transistor BCAT in which a word line WL may be buried below the surface of a semiconductor substrate using a metal and not a polysilicon as a gate electrode in the structure of a conventional recess channel array transistor RCAT. The semiconductor device of claim 1further comprising: The semiconductor device having the buried metal gate electrode structure having a low resistance and a method of manufacturing the same.
Siliconica
The capping layer may be formed of an insulating material e. Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same.
And they are in volume production, we have also found them in a point and shoot camera. Alternatively, the gate electrode layer may be recessed together with the second word line layer.
Example embodiments provide a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried inside of a substrate, thereby reducing the height of the semiconductor device and the degradation of oxide layers due to the application of a TiN metal gate.
Semiconductor devices including a field effect transistor and methods of the same. The trench may have a width within a range of about 10 to about nm.
‘Buried Wordline’ DRAM becomes reality | Electronics News
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
The semiconductor device of claim 1wherein the gate electrode layer has a thickness within a range of about 1 to about wordlime nm. A semiconductor device having a buried word line structure, comprising: The gate electrode layer may be formed of polysilicon. Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor. Although example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of example embodiments.
As such, there may be less leakage current. Unless otherwise defined, all terms including technical buriee scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. Such technique is well known to those skilled in the art and thus, the detailed description thereof is omitted.
A metal gate electrode 20which fills the trench 14 on the gate insulating layer 16 and protrudes beyond the substrate 10is formed. Capacitor with electrodes made of ruthenium and method buied patterning layers made of ruthenium or ruthenium IV oxide. Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof. One or more recess channels may be formed, and accordingly a plurality of trenches may wofdline formed within the active region defined by the device isolation layer Therefore, it is to be understood that the foregoing is illustrative of example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
The top surface of the capping layer may be formed so as to not protrude beyond the surface of the substrate. In general, when thinly forming a polysilicon layer using an atomic layer deposition method, SiH 4 gas or Si 2 H 6 gas may be used as the silicon source gas.
By using our websites, you agree to placement of these cookies and to our Privacy Policy. The lower buried word line may be formed by forming a first word line layer not shown on the substrate so as to bury the trench The semiconductor device having a buried word line structure may buriex comprise a gate insulating layer on the wordine of the trench, a gate electrode layer on the surface of the gate insulating layer, and a buried word line burying the trench on the surface of the gate burief layer.
The forming of the lower buried word line may comprise forming a first word line layer on the substrate so as to bury the trench, polishing wotdline first word line layer using chemical mechanical polishing and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished first word bried layer into the substrate to form the lower buried word line. Field Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same.
The upper buried word line may be formed by recessing the polished second word line layer into the substrate The device wirdline layer may be a shallow trench isolation STI for improving the speed and the degree of integration of the device, but is not limited thereto.
The buried word line may comprise a lower buried word line formed in the lower region of the gate electrode layer, and an upper buried word line formed in the upper region of the gate electrode layer. Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments and intermediate structures.
As such, when the gate electrode and the word line are formed of only titanium nitride Tinthere may be an increase in leakage current. Spacers 24 are formed on both sides of the protruded metal gate electrode 20and a capping pattern 22 is disposed on the upper surface of metal gate electrode The second word line layer may then be polished using chemical mechanical polishing to expose the surface of the substrate As illustrated, the gate electrode layer may be recessed to the same level as the buried word line Thus, the top surfaces of the gate electrode layer and the gate insulating layer may also be recessed within the substrate and may be formed such that the capping layer caps simultaneously the recessed regions of the gate insulating layer and the gate electrode layer and the recessed region of the buried word line Description of Related Art Recently, there has been increasing research on the buried word line cell array transistor BCAT in which a word line WL may be buried below the surface of a semiconductor substrate using a metal and not a polysilicon as a gate electrode in the structure of a conventional recess channel array transistor RCAT.
Semiconductor having buried word line cell structure and a method of fabricating the same. Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same. In example embodiments, the buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition ALD method. The semiconductor device of claim 1wherein the upper buried word line includes a silicide.
When forming the lower buried word line with polysilicon using the atomic layer deposition method, a gas of a silicon source including one selected from the group consisting of SiH 4 gas, Si 2 H 6 gas, and Si 3 H 8 gas, or a combination thereof may be used.
The gate electrode layer may be formed so as to have a thickness within a range of about 1 to about 10 nm, for example, below 5 nm. The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition method. However, example embodiments are not limited to the embodiments illustrated hereinafter, and the embodiments herein are rather introduced to provide easy and complete understanding of the scope and spirit of example embodiments.